 module out_data_shift(
		input	wire			resetb,
		input   wire			out_clk,
		input   wire	[255:0]	read_data,
		input   wire			data_load_req,
		input   wire			data_shift_req,
		input   wire			r_shift_req,
		input   wire	[3:0]	data_bit_sel,
		output  reg		[15:0]	data_bit
		);
		
reg     [15:0]  send_data0,send_data1,send_data2,send_data3,send_data4,send_data5,send_data6,send_data7; 
reg     [15:0]  send_data8,send_data9,send_data10,send_data11,send_data12,send_data13,send_data14,send_data15; 

always @(posedge out_clk or negedge resetb)
        if (resetb == 0) begin    
		send_data0<=0;
		send_data1<=0;
		send_data2<=0;
		send_data3<=0;
		send_data4<=0;
		send_data5<=0;
		send_data6<=0;
		send_data7<=0;
		send_data8<=0;
		send_data9<=0;
		send_data10<=0;
		send_data11<=0;
		send_data12<=0;
		send_data13<=0;
		send_data14<=0;
		send_data15<=0;
        	end
        else if (data_load_req == 1) begin
		send_data0<={read_data[15:0] };
		send_data1<={read_data[31:16]};
		send_data2<={read_data[47:32]};
		send_data3<={read_data[63:48]};
		send_data4<={read_data[79:64]};
		send_data5<={read_data[95:80]};
		send_data6<={read_data[111:96]};
		send_data7<={read_data[127:112]}; 
		send_data8<={read_data[143:128]};
		send_data9<={read_data[159:144]}; 
		send_data10<={read_data[175:160] };
		send_data11<={read_data[191:176]};
		send_data12<={read_data[207:192]};
		send_data13<={read_data[223:208]};
		send_data14<={read_data[239:224]};
		send_data15<={read_data[255:240]};
		end
	else if (data_shift_req == 1) begin
		send_data0<={send_data0[14:0],1'b0}; 
		send_data1<={send_data1[14:0],1'b0}; 
		send_data2<={send_data2[14:0],1'b0}; 
		send_data3<={send_data3[14:0],1'b0}; 
		send_data4<={send_data4[14:0],1'b0}; 
		send_data5<={send_data5[14:0],1'b0}; 
		send_data6<={send_data6[14:0],1'b0}; 
		send_data7<={send_data7[14:0],1'b0}; 
		send_data8<={send_data8[14:0],1'b0}; 
		send_data9<={send_data9[14:0],1'b0}; 
		send_data10<={send_data10[14:0],1'b0}; 
		send_data11<={send_data11[14:0],1'b0}; 
		send_data12<={send_data12[14:0],1'b0}; 
		send_data13<={send_data13[14:0],1'b0}; 
		send_data14<={send_data14[14:0],1'b0}; 
		send_data15<={send_data15[14:0],1'b0}; 
		end
	else if (r_shift_req == 1)begin
		send_data0<={send_data0[14:1]}; 
		send_data1<={send_data1[14:1]}; 
		send_data2<={send_data2[14:1]}; 
		send_data3<={send_data3[14:1]}; 
		send_data4<={send_data4[14:1]}; 
		send_data5<={send_data5[14:1]}; 
		send_data6<={send_data6[14:1]}; 
		send_data7<={send_data7[14:1]}; 
		send_data8<={send_data8[14:1]}; 
		send_data9<={send_data9[14:1]}; 
		send_data10<={send_data10[14:1]}; 
		send_data11<={send_data11[14:1]}; 
		send_data12<={send_data12[14:1]}; 
		send_data13<={send_data13[14:1]}; 
		send_data14<={send_data14[14:1]}; 
		send_data15<={send_data15[14:1]}; 
		end
		
always @(posedge out_clk) begin
	data_bit[0]<=send_data0[data_bit_sel];
	data_bit[1]<=send_data1[data_bit_sel];
	data_bit[2]<=send_data2[data_bit_sel];
	data_bit[3]<=send_data3[data_bit_sel];
	data_bit[4]<=send_data4[data_bit_sel];
	data_bit[5]<=send_data5[data_bit_sel];
	data_bit[6]<=send_data6[data_bit_sel];
	data_bit[7]<=send_data7[data_bit_sel];
	data_bit[8]<=send_data8[data_bit_sel];
	data_bit[9]<=send_data9[data_bit_sel];
	data_bit[10]<=send_data10[data_bit_sel];
	data_bit[11]<=send_data11[data_bit_sel];
	data_bit[12]<=send_data12[data_bit_sel];
	data_bit[13]<=send_data13[data_bit_sel];
	data_bit[14]<=send_data14[data_bit_sel];
	data_bit[15]<=send_data15[data_bit_sel];
	end
	
endmodule